1. Field of the Invention
The present invention relates to a NAND flash memory and a memory system.
2. Background Art
In a nonvolatile memory cell of a NAND flash memory and so on, electrons are trapped in an oxide film by applying a high electric field. Thus the threshold voltage of the memory cell is changed and data is written according to the threshold voltage, and then the data is read using a difference in the threshold voltage.
When the electrons are permanently trapped in the oxide film, the data is held without any problems. However, the electrons trapped in the oxide film are drawn to a stable neutral threshold voltage with the passage of time.
The drawing of electrons changes the threshold voltage of the memory cell. Thus the data is erroneously read and problems occur when the data is held.
Even if the threshold voltage can be set at a higher threshold distribution to write data, the probability of erroneous writing may increase. For this reason, the threshold voltage cannot be set at quite a high threshold distribution to write data.
Therefore, for example, in the case of multilevel data which is octal or hexadecimal, an interval between threshold distributions is smaller than in binary or four-valued data. Although binary or four-valued data is not disadvantageous, octal or hexadecimal data is more likely to cause some problems when the data is held.
In a NAND flash memory, for example, two memory cells M0 and M31 disposed on both ends of 32 memory cells connected in series are respectively adjacent to a source-side selection gate transistor SGS which is connected between the memory cells and a common source line and a drain-side selection transistor SGD which is connected between the other end of the memory cells and a bit line.
Therefore, when writing is not performed on the memory cells M0 and M31, the memory cells M0 and M31 are respectively adjacent to the source-side selection gate transistor SGS biased to 0 V (VSGD) and the drain-side selection transistor SGD connected between the other end of the memory cells and the bit line.
Thus, for example, a high electric field of a boosted channel and a ground VSS is applied between the source-side selection gate transistor SGS and the memory cell M0, so that tunnel current is generated and erroneous writing occurs on the memory cell M0. The same problem may occur between the drain-side selection transistor SGD and the memory cell M31.
This phenomenon is more likely to occur as a writing voltage increases and a distance between the source-side selection gate transistor SGS and the memory cell M0 decreases (between the drain-side selection transistor SGD and the memory cell M31).
In recent years, a distance between a memory cell and the source-side selection gate transistor SGS (drain-side selection transistor SGD) has been reduced in response to smaller design rules of semiconductor process technology.
Consequently, erroneous writing is more likely to occur.
Thus in the prior art, for example, cells adjacent to the source-side selection gate transistor SGS and a memory cell M (drain-side selection transistor SGD) are dummy cells.
A NAND flash memory of the prior art includes, for example, a monitor bit having a smaller threshold margin in data holding characteristics than in a nonvolatile memory cell used for reading and writing data (for example, see Japanese Patent Laid-Open No. 2000-173275).
In the NAND flash memory of the prior art, when defective data is detected in the monitor bit, a sector containing the monitor bit is replaced with another sector.